During the testing of a memory, it is common to apply a plurality of patterns to the memory which may be based on the physical structure of the cell array. However, a common concern during testing is whether the patterns have been applied correctly to the memory based on the physical structure of the cell array. For example, in a cell array, it may be beneficial to write a checkerboard pattern (e.g., alternating 1's and 0's), where adjacent cells have different values. In order to write a checkerboard pattern, one must have knowledge of the cell array structure (e.g., what does it look like).
In practice, there is no common method for producing a cell layout. For example, a cell structure may have multiple columns per data bit, with a different addressing structure across the columns. The different cell arrays, however, have to be taken into account during testing, which may be difficult due to the number of possible cell structures. Previously, when determining a memory failure, it was common to write values in a particular manner and then read the same values in the same manner. However, due to the different possible cell structure, there was no way to determine if the correct cell structure was applied to the memory. This is because a failure will generally not occur when reading the same values that were previously written. Thus, in order to determine a failure, a representation of the physical cell array may need to be created.
Thus, it may be beneficial to provide an exemplary system, method, and computer-accessible medium for verifying results in simulation through simulation add-on to support visualization of selected memory contents in real time, which may overcome at least some of the deficiencies described herein above.